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| MC14541B Programmable Timer The MC14541B programmable timer consists of a 16-stage binary counter, an integrated oscillator for use with an external capacitor and two resistors, an automatic power-on reset circuit, and output control logic. Timing is initialized by turning on power, whereupon the power-on reset is enabled and initializes the counter, within the specified VDD range. With the power already on, an external reset pulse can be applied. Upon release of the initial reset command, the oscillator will oscillate with a frequency determined by the external RC network. The 16-stage counter divides the oscillator frequency (fosc) with the nth stage frequency being fosc/2n. * Available Outputs 28, 210, 213 or 216 * Increments on Positive Edge Clock Transitions * Built-in Low Power RC Oscillator ( 2% accuracy over temperature range and 20% supply and 3% over processing at < 10 kHz) * Oscillator May Be Bypassed if External Clock Is Available (Apply external clock to Pin 3) * External Master Reset Totally Independent of Automatic Reset Operation * Operates as 2n Frequency Divider or Single Transition Timer * Q/Q Select Provides Output Logic Level Flexibility * Reset (auto or master) Disables Oscillator During Resetting to Provide No Active Power Dissipation * Clock Conditioning Circuit Permits Operation with Very Slow Clock Rise and Fall Times * Automatic Reset Initializes All Counters On Power Up * Supply Voltage Range = 3.0 Vdc to 18 Vdc with Auto Reset Supply Voltage Range = Disabled (Pin 5 = VDD) Supply Voltage Range = 8.5 Vdc to 18 Vdc with Auto Reset Supply Voltage Range = Enabled (Pin 5 = VSS) MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.) Symbol VDD Vin, Vout Iin Iout PD TA Tstg TL Parameter DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) Input Current (DC or Transient) Output Current (DC or Transient) Power Dissipation, per Package (Note 3.) Ambient Temperature Range Storage Temperature Range Lead Temperature (8-Second Soldering) Value - 0.5 to +18.0 - 0.5 to VDD + 0.5 10 (per Pin) 45 (per Pin) 500 - 55 to +125 - 65 to +150 260 Unit V MC14541BDTR2 V MC14541BF mA mA mW C C C MC14541BFEL SOEIAJ-14 SOEIAJ-14 See Note 1. See Note 1. TSSOP-14 2500/Tape & Reel http://onsemi.com MARKING DIAGRAMS MC14541BCP AWLYYWW 1 14 14541B AWLYWW 1 14 TSSOP-14 DT SUFFIX CASE 948G 14 SOEIAJ-14 F SUFFIX CASE 965 1 MC14541B AWLYWW 14 541B ALYW PDIP-14 P SUFFIX CASE 646 SOIC-14 D SUFFIX CASE 751A 14 1 A = Assembly Location WL or L = Wafer Lot YY or Y = Year WW or W = Work Week ORDERING INFORMATION Device MC14541BCP MC14541BD MC14541BDR2 MC14541BDT Package PDIP-14 SOIC-14 SOIC-14 TSSOP-14 Shipping 2000/Box 55/Rail 2500/Tape & Reel 96/Rail 1. For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative. This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. 2. Maximum Ratings are those values beyond which damage to the device may occur. 3. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/_C From 65_C To 125_C (c) Semiconductor Components Industries, LLC, 2000 v v 1 March, 2000 - Rev. 6 Publication Order Number: MC14541B/D MC14541B PIN ASSIGNMENT Rtc Ctc RS NC AR MR VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD B A NC MODE Q/Q SEL Q NC = NO CONNECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 VIH 5.0 10 15 IOH Source 5.0 10 15 IOL 5.0 10 15 15 -- 5.0 10 15 10 15 5.0 10 15 - 7.96 - 4.19 - 16.3 1.93 4.96 19.3 -- -- -- -- -- -- -- -- -- -- -- -- -- 0.1 -- 5.0 10 20 250 500 - 6.42 - 3.38 - 13.2 1.56 4.0 15.6 -- -- -- -- -- -- -- - 12.83 - 6.75 - 26.33 3.12 8.0 31.2 0.00001 5.0 0.005 0.010 0.015 30 82 -- -- -- -- -- -- 0.1 7.5 5.0 10 20 250 500 - 4.49 - 2.37 - 9.24 1.09 2.8 10.9 -- -- -- -- -- -- -- -- -- -- -- -- -- 1.0 -- 150 300 600 1500 2000 mAdc 3.5 7.0 11 -- -- -- 3.5 7.0 11 2.75 5.50 8.25 -- -- -- 3.5 7.0 11 -- -- -- mAdc - 55_C 25_C 125_C Characteristic Symbol VOL Min -- -- -- 4.95 9.95 14.95 -- -- -- Max Min -- -- -- 4.95 9.95 14.95 -- -- -- Typ (4.) 0 0 0 5.0 10 15 2.25 4.50 6.75 Max Min -- -- -- 4.95 9.95 14.95 -- -- -- Max Unit Vdc Output Voltage Vin = VDD or 0 "0" Level 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 Vdc "1" Level Vin = 0 or VDD Input Voltage "0" Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) "1" Level (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Input Current Input Capacitance (Vin = 0) Quiescent Current (Pin 5 is High) Auto Reset Disabled Auto Reset Quiescent Current (Pin 5 is low) Supply Current (5.) (6.) (Dynamic plus Quiescent) VIL VOH Vdc Vdc Sink Iin Cin IDD Adc pF Adc IDDR ID Adc Adc ID = (0.4 A/kHz) f + IDD ID = (0.8 A/kHz) f + IDD ID = (1.2 A/kHz) f + IDD 4. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. 5. The formulas given are for the typical characteristics only at 25_C. 6. When using the on chip oscillator the total supply current (in Adc) becomes: IT = ID + 2 Ctc VDD f x 10-3 where ID is in A, Ctc is in pF, VDD in Volts DC, and f in kHz. (see Fig. 3) Dissipation during power-on with automatic reset enabled is typically 50 A @ VDD = 10 Vdc. ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) http://onsemi.com 2 MC14541B IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII SWITCHING CHARACTERISTICS (7.) (CL = 50 pF, TA = 25_C) Characteristic Output Rise and Fall Time tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns Symbol tTLH, tTHL VDD 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 Min -- -- -- -- -- -- -- -- -- 900 300 225 -- -- -- 900 300 225 420 200 200 Typ (8.) 100 50 40 Max 200 100 80 Unit ns Propagation Delay, Clock to Q (28 Output) tPLH, tPHL = (1.7 ns/pF) CL + 3415 ns tPLH, tPHL = (0.66 ns/pF) CL + 1217 ns tPLH, tPHL = (0.5 ns/pF) CL + 875 ns Propagation Delay, Clock to Q (216 Output) tPHL, tPLH = (1.7 ns/pF) CL + 5915 ns tPHL, tPLH = (0.66 ns/pF) CL + 3467 ns tPHL, tPLH = (0.5 ns/pF) CL + 2475 ns Clock Pulse Width tPLH tPHL s 3.5 1.25 0.9 6.0 3.5 2.5 300 100 85 1.5 4.0 6.0 300 100 85 210 100 100 10.5 3.8 2.9 s 18 10 7.5 -- -- -- 0.75 2.0 3.0 -- -- -- -- -- -- ns tPHL tPLH tWH(cl) Clock Pulse Frequency (50% Duty Cycle) fcl MHz MR Pulse Width tWH(R) ns Master Reset Removal Time trem ns 7. The formulas given are for the typical characteristics only at 25_C. 8. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. VDD VDD PULSE GENERATOR RS AR Q/Q SELECT MODE A B MR VSS PULSE GENERATOR RS AR Q/Q SELECT MODE A B MR VSS Q CL Q CL (Rtc AND Ctc OUTPUTS ARE LEFT OPEN) 20 ns 90% 50% 10% 50% DUTY CYCLE Q tTLH 20 ns RS 20 ns 90% 50% 10% tPLH 50% 90% 10% 50% tTHL 20 ns 50% tPHL Figure 1. Power Dissipation Test Circuit and Waveform Figure 2. Switching Time Test Circuit and Waveforms http://onsemi.com 3 MC14541B EXPANDED BLOCK DIAGRAM A 12 B 13 1 OF 4 MUX 8Q Rtc 1 Ctc 2 RS 3 OSC RESET 8-STAGE 8 2 C COUNTER RESET 210 213 216 C 8-STAGE COUNTER RESET AUTO RESET 5 POWER-ON RESET 6 MASTER RESET VDD = PIN 14 VSS = PIN 7 10 MODE 9 Q/Q SELECT FREQUENCY SELECTION TABLE Number of Counter Stages n 13 10 8 16 Count 2n 8192 1024 256 65536 Mode, 10 TRUTH TABLE State Pin Auto Reset, 5 0 Auto Reset Operating Timer Operational Output Initially Low After Reset Single Cycle Mode 1 Auto Reset Disabled Master Reset On Output Initially High After Reset Recycle Mode A 0 0 1 1 B 0 1 0 1 Master Reset, 6 Q / Q, 9 3 TO CLOCK CIRCUIT INTERNAL RESET 2 Ctc RS RTC 1 Figure 3. Oscillator Circuit Using RC Configuration http://onsemi.com 4 MC14541B TYPICAL RC OSCILLATOR CHARACTERISTICS 8.0 VDD = 15 V f, OSCILLATOR FREQUENCY (kHz) 4.0 FREQUENCY DEVIATION (%) 0 10 V - 4.0 - 8.0 - 12 - 16 - 55 RTC = 56 k, C = 1000 pF RS = 0, f = 10.15 kHz @ VDD = 10 V, TA = 25C RS = 120 k, f = 7.8 kHz @ VDD = 10 V, TA = 25C 100 50 20 10 5.0 2.0 1.0 0.5 0.2 0.1 1.0 k 0.0001 10 k 100 k RTC, RESISTANCE (OHMS) 0.001 0.01 C, CAPACITANCE (F) 1.0 m 0.1 f AS A FUNCTION OF C (RTC = 56 k) (RS = 120 k) VDD = 10 V f AS A FUNCTION OF RTC (C = 1000 pF) (RS 2RTC) 5.0 V - 25 0 25 50 75 TA, AMBIENT TEMPERATURE (C) 100 125 Figure 4. RC Oscillator Stability Figure 5. RC Oscillator Frequency as a Function of Rtc and Ctc OPERATING CHARACTERISTICS With Auto Reset pin set to a "0" the counter circuit is initialized by turning on power. Or with power already on, the counter circuit is reset when the Master Reset pin is set to a "1". Both types of reset will result in synchronously resetting all counter stages independent of counter state. Auto Reset pin when set to a "1" provides a low power operation. The RC oscillator as shown in Figure 3 will oscillate with a frequency determined by the external RC network i.e., f= 1 2.3 RtcCtc if (1 kHz v f v 100 kHz) and RS 2 Rtc where RS 10 k The time select inputs (A and B) provide a two-bit address to output any one of four counter stages (28, 210, 213 and 216). The 2n counts as shown in the Frequency Selection Table represents the Q output of the Nth stage of the counter. When A is "1", 216 is selected for both states of B. However, when B is "0", normal counting is interrupted and the 9th counter stage receives its clock directly from the oscillator (i.e., effectively outputting 28). The Q/Q select output control pin provides for a choice of output level. When the counter is in a reset condition and Q/Q select pin is set to a "0" the Q output is a "0", correspondingly when Q/Q select pin is set to a "1" the Q output is a "1". When the mode control pin is set to a "1", the selected count is continually transmitted to the output. But, with mode pin "0" and after a reset condition the RS flip-flop (see Expanded Block Diagram) resets, counting commences, and after 2n-1 counts the RS flip-flop sets which causes the output to change state. Hence, after another 2n-1 counts the output will not change. Thus, a Master Reset pulse must be applied or a change in the mode pin level is required to reset the single cycle operation. DIGITAL TIMER APPLICATION Rtc 1 Ctc RS AR MR INPUT tMR 2 3 4 5 6 7 14 13 12 11 10 9 8 OUTPUT MODE Q/Q VDD VDD B A N.C. NC When Master Reset (MR) receives a positive pulse, the internal counters and latch are reset. The Q output goes high and remains high until the selected (via A and B) number of clock pulses are counted, the Q output then goes low and remains low until another input pulse is received. This "one shot" is fully retriggerable and as accurate as the input frequency. An external clock can be used (pin 3 is the clock input, pins 1 and 2 are outputs) if additional accuracy is needed. Notice that a setup time equal to the desired pulse width output is required immediately following initial power up, during which time Q output will be high. t + tMR http://onsemi.com 5 MC14541B PACKAGE DIMENSIONS P SUFFIX PLASTIC DIP PACKAGE CASE 646-06 ISSUE M 14 8 B 1 7 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.290 0.310 --- 10_ 0.015 0.039 MILLIMETERS MIN MAX 18.16 18.80 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.37 7.87 --- 10_ 0.38 1.01 A F N -T- SEATING PLANE L C K H G D 14 PL 0.13 (0.005) M J M DIM A B C D F G H J K L M N D SUFFIX PLASTIC SOIC PACKAGE CASE 751A-03 ISSUE F -A- 14 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. -B- 1 7 P 7 PL 0.25 (0.010) M B M G C R X 45 _ F -T- SEATING PLANE D 14 PL 0.25 (0.010) M K TB S M A S J DIM A B C D F G J K M P R MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019 http://onsemi.com 6 MC14541B PACKAGE DIMENSIONS DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948G-01 ISSUE O 14X K REF NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS INCHES DIM MIN MAX MIN MAX A 4.90 5.10 0.193 0.200 B 4.30 4.50 0.169 0.177 C --- 1.20 --- 0.047 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC H 0.50 0.60 0.020 0.024 J 0.09 0.20 0.004 0.008 J1 0.09 0.16 0.004 0.006 K 0.19 0.30 0.007 0.012 K1 0.19 0.25 0.007 0.010 L 6.40 BSC 0.252 BSC M 0_ 8_ 0_ 8_ 0.10 (0.004) 0.15 (0.006) T U S M TU S V S N 2X L/2 14 8 0.25 (0.010) M L PIN 1 IDENT. 1 7 B -U- N F DETAIL E K K1 J J1 0.15 (0.006) T U S A -V- C 0.10 (0.004) -T- SEATING PLANE D G H DETAIL E http://onsemi.com 7 CCC EE CCC EE SECTION N-N -W- MC14541B PACKAGE DIMENSIONS F SUFFIX PLASTIC EIAJ SOIC PACKAGE CASE 965-01 ISSUE O 14 8 LE Q1 E HE M_ L DETAIL P 1 7 Z D e A VIEW P NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE 0.50 LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 1.42 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.056 c b 0.13 (0.005) M A1 0.10 (0.004) ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORDERING INFORMATION NORTH AMERICA Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: ONlit@hibbertco.com Fax Response Line: 303-675-2167 or 800-344-3810 Toll Free USA/Canada N. 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